二位元全加器 Verilog

module top
  integer ia0,ia1,ib0,ib1
  reg  A0, A1, B0, B1, cin0
  wire s0, s1, co1

  adder2 ad1(s0, s1, co1, A0, A1, B0, B1, cin0)

  initial
    begin
      cin0 = 0
      for (ia0=0; ia0<=1; ia0 = ia0 + 1)
        begin
          A0 = ia0;
          for (ib0=0; ib0<=1; ib0 = ib0 + 1)
            begin
              B0 = ib0;
              for (ia1=0; ia1<=1; ia1 = ia1 + 1)
               begin
                 A1 = ia1;
                 for (ib1=0; ib1<=1; ib1 = ib1 + 1)
                  begin
                    B1 = ib1;
                    #10 $display("A0=%d B0=%d A1=%d B1=%d   s0=%d s1=%d co1=%d",A0,B0,A1,B1,s0,s1,co1)
                  end
               end
            end
        end
    end
endmodule

module adder2(sun0, sun1, cout1, A0, A1, B0, B1, cin0);
 output sun0,sun1,cout1;
 input A0,A1,B0,B1,cin0;
 adder1 a1 (sun0, cout0, A0, B0, cin0);
 adder1 a2 (sun1, cout1, A1, B1, cout0);
endmodule

module adder1(sun, cout, A, B, cin);
 output cout,sun;
 input A,B,cin;
 xor x1 (x, A, B);
 xor x2 (sun, x, cin);
 and a1 (y, A, B);
 and a2 (z, cin, x);
 xor x3 (cout, y, z); 
endmodule

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